1. Field of the Invention
The present invention relates to a circuit arrangement comprising a matrix-shaped memory arrangement for variably adjustable delay of digital signals in which 3-transistor cells having overlapping write/read cycles are provided as storage elements. A row selector which is clocked controlled by an input data clock, continually settable and resettable at any time is provided. The row selector comprises, respectively, two signal outputs per selection stage which are offset in phase relative to one another and which respectively select a write word line or a read word line provided per row of the matrix. Two separate bit lines, namely a write bit line and a read bit line are provided per column, these being respectively interconnected with all memory cells of a column. A disconnectible storage amplifier is provided per column and has an input connected to the read bit line of a column and an output connected to the write bit line of the following column and serving as a data output. A data input for the data signals to be delayed is connected to the write bit line of the first column and to an undelayed data output. A reset input is connected to setting inputs of a first element of the row selector as well as to reset inputs of the remaining elements of the row selector as in the aforementioned application Ser. No. 828,512.
2. Description of the Prior Art
Equipment with whose assistance define delays of digital data streams can be effected are frequently required in the field of digital signal processing, as well as in the field of communications technology. For example, defined delays are employed for time compensation. Given a constant number of desired delay clocks, an arrangement having a shift register is generally available as a delay device. When, however, the delay is to be variably adjustable, certain problems occur in the employment of shift registers.
It is also known to delay data streams in defined fashion by way of an arrangement of standard circuits and storage modules. In such an arrangement, the component parts of the data stream are deposited in a freely-adjustable memory. This memory is driven by a decoder which is, in turn, driven by one (or more) counters. The duration of the delay is thereby established by the duration of the counter reset pulses. Since the memory cells of such freely-addressable memories can only respectively read or write per clock, the necessity thereby occurs that the memories are either operated with twice the clock rate or switching must be carried out back and forth between two memory units in a multiplex mode. The first solution of this problem has the disadvantage that the maximum data clock frequency can only be half as great as the maximum memory cycle frequency. The solution of the latter problem requires involved circuits for address control and a required reordering of the data. For an integratible realization of such a circuit arrangement, moreover, disadvantages arise as a consequence of the high space requirement of the necessary multiplexers and because of the extensive wiring required.
It was the object of the aforementioned application Ser. No. 828,512 to provide a circuit arrangement by way of which defined, variably adjustable delays can be achieved, this be realizable by way of an integrated circuit arrangement which requires a low surface requirement and allows higher data rates in comparison to the known art. In particular, the object was comprised in creating a circuit arrangement which is particularly suitable for integration in metal-oxide-semiconductor (MOS) technology. In application Ser. No. 828,512, the object was achieved, according to that invention, by the provision of a circuit arrangement for a variably adjustable time delay of digital signals which comprises a matrix-shaped memory and which is particularly characterized in that known three-transistor memory cells having overlapping write/read cycles are provided as storage elements, in that a continuously steppable row selector is provided which can be reset at any time and which is clocked by the input data clock. The row selector comprises two respective, mutually phase offset signal outputs per selection stage which respectively drive a write word line or a read word line per row of the matrix-shaped memory, and in that two separate bit lines are provided per column, a write bit line and a read bit line which are respectively interconnected to all memory cells of a column. Furthermore, a disconnectible storage amplifier is provided per column and has an input connected to the read bit line of the column assigned thereto and an output connected to the write bit line of the following column and serving as a data output. A data input for the data signals to be delayed is connected to the write bit line of the first column and to an undelayed data output. A reset input is connected to setting inputs of the first element of the row selector as well as to the reset inputs of the remaining elements of the row selector. The chronological spacing between reset pulses is selected such that it equals the required delay time which is to be set between the undelayed data output and the first delayed data output.